NAND EEPROM based non-volatile flash memory architecture is described in U.S. Pat. No. 5,568,420, filed Nov. 30, 1994, and entitled "Nonvolatile Semiconductor Memory Device"; and on pages 119-120 and 124-126 of Semiconductor Memories (ISBN number: 0-7803-1000-4), which are incorporated herein by reference in their entirety.
One problem with the conventional NAND array memory device is described with reference to FIG. 1 which is a cross sectionl adiagram of a conventional floating gate memory cell 100 of a NAND array. The memory cell 100 is a floating gate transistor having a control gate 102 separated from a polycrystalline silicon floating gate 106 by an upper insulating layer 104, the floating gate 106 being separated from a substrate 110 by a lower insulating layer 108. The substrate 110 includes an n+source region 112, a p-doped body region 114, and an n+drain region 116 as in a conventional NMOS enhancement mode transistor.
In order to program the conventional floating gate memory cell 100, control gate 102 is biased at a relatively high voltage of approximately 20 volts while body region 114 is grounded. The high voltage on the control gate 102 induces electrons from body region 114 to tunnel through the lower insulation layer 108 and into floating gate 106 through a conventionally known process called Fowler-Nordheim tunneling. The floating gate 106 accumulates negative charge thereby increasing the threshold voltage of the memory cell 100. Erasing occurs by biasing the body region 114 at a high voltage of approximately 20 volts while the control gate 102 is grounded causing the electrons from floating gate 106 to tunnel through lower insulation layer 108 and into the body region 114.
This conventional memory cell structure and process require that the peripheral delivery circuitry such as decoders and charge pumps contain devices capable of processing and producing at least 20 volts. The design for circuits capable of processing and producing high voltages of, for example, 20 volts are more complex, require more space, and have more complex transistor technology than do circuits for lower voltage applications.
Therefore, what is desired is an improved structure and method for reducing the voltage requirements of the peripheral circuitry for delivery of voltages to the control gate and body region of a floating gate memory cell in a NAND array.